2014

• M. Russold, S. Lewis, L. Abu-Saleh, J.M. Cardona Audi, M. Hahn, M. Schiestl, R. Ruff, D. Schroeder, B. Taghizadeh, S. Plümer, K.-P. Hoffmann, W. Krautschneider, A. Gail, T. Meiners, H. Lanmüller, O. Aszmann, H. Dietl
  Development of a fully implantable EMG measurement system: Status report on the MyoPlant project
  In Tagungsband "BMT 2014", 2014, p. S1085
  Hannover, 8.-10.2014
  Abstract:
  
  BibTeX:
  @inproceedings{Russold:BMT:2014,
  author = {M. Russold and S. Lewis and L. Abu-Saleh and J.M. Cardona Audi and M. Hahn and M. Schiestl and R. Ruff and D. Schroeder and B. Taghizadeh and S. Pl{\"u}mer and K.-P. Hoffmann and W. Krautschneider and A. Gail and T. Meiners and H. Lanm{\"u}ller and O. Aszmann and H. Dietl},
  title = {{D}evelopment of a fully implantable {E}{M}{G} measurement system: {S}tatus report on the {M}yo{P}lant project},
  year = {2014},
  month = {10},
  booktitle = {BMT 2014},
  note = {Hannover, 8.-10.2014},
  pages = {S1085} }
  [BibTeX]
  
  
• Aljoscha Reinert, Jan Loitz, Dietmar Schroeder, Wolfgang Krautschneider
  Forearm motor point characterization for smart electrode array shaping
  In Tagungsband "BMT 2014", 2014, p. S1031
  Hannover, 8.-10.10.2014
  Abstract:
  
  BibTeX:
  @inproceedings{Reinert:BMT:2014,
  author = {Aljoscha Reinert and Jan Loitz and Dietmar Schroeder and Wolfgang Krautschneider},
  title = {{F}orearm motor point characterization for smart electrode array shaping},
  year = {2014},
  month = {10},
  booktitle = {BMT 2014},
  note = {Hannover, 8.-10.10.2014},
  pages = {S1031} }
  [BibTeX]
  
  
• Iyappan Subbiah, Andreas Süss, Andrey Kravchenko, Bedrich Hosticka, Wolfgang Krautschneider
  A Low Noise Saturation-Stacked Bandgap Reference for Image Sensor Applications
  In Tagungsband "Proc. International Semiconductor Conference (CAS) 2014", 2014, p. 247-250
  Sinaia, 13.-15.10.2014
  Abstract:
  Abstract: A novel architecture for a bandgap voltage reference is presented in this paper. The voltage reference, designed for image sensor applications, is primarily targeted for a low-noise operation along with other practical constraints such as high power supply rejection, temperature immunity and short start-up time. The analysis and operation of the circuit is discussed and the trade-offs involved in the implementation aspects are examined. The measurement results of the fabricated circuit in a 0.35-μm CMOS process show a noise voltage level of 450 nV/√Hz at 10 Hz, a temperature coefficient of 14 ppm/K and a PSRR of 52 dB.
  BibTeX:
  @inproceedings{Subbiah:Bandgap:2014,
  author = {Iyappan Subbiah and Andreas S{\"u}ss and Andrey Kravchenko and Bedrich Hosticka and Wolfgang Krautschneider},
  title = {{A} {L}ow {N}oise {S}aturation-{S}tacked {B}andgap {R}eference for {I}mage {S}ensor {A}pplications},
  year = {2014},
  month = {10},
  booktitle = {Proc. International Semiconductor Conference (CAS) 2014},
  note = {Sinaia, 13.-15.10.2014},
  pages = {247-250} }
  [Abstract] [BibTeX] [DOI]
  
  
• C. Riggert and M. Ziegler and D. Schroeder and W.H. Krautschneider and H. Kohlstedt
  MemFlash device: floating gate transistors as memristive devices for neuromorphic computing
  Artikel in "Semiconductor Science and Technology", vol. 29, Nr. 10, p. 104011, 2014
  Abstract:
  Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.
  BibTeX:
  @article{Riggert:SST:2014,
  author = {C. Riggert and M. Ziegler and D. Schroeder and W.H. Krautschneider and H. Kohlstedt},
  title = {{M}em{F}lash device: floating gate transistors as memristive devices for neuromorphic computing},
  year = {2014},
  month = {09},
  journal = {Semiconductor Science and Technology},
  number = {10},
  pages = {104011},
  volume = {29} }
  [Abstract] [BibTeX] [DOI]
  
  
• Zhihao Pan and Schroeder, D. and Holland, S. and Krautschneider, W.H.
  Understanding and Modeling of Diode Voltage Overshoots During Fast Transient ESD Events
  Artikel in "IEEE Transactions on Electron Devices", vol. 61, Nr. 8, p. 2682-2689, 2014
  Abstract:
  Diodes in forward direction exhibit excellent ESD ruggedness and are thus widely used in both discrete and on-chip electro-static discharge (ESD) protection devices. Due to the conductivity modulation under an ESD stress, a transient voltage overshoot is observed at the beginning of a fast discharge event. Since the voltage overshoot can be harmful, understanding the origin of the overshoot is crucial to design optimized protection diodes. In this paper, it will be shown that existing models can result in much underestimated overshoot voltage, especially for diodes with a large lowly doped region. This can be attributed to the negligence of transient charge distribution in the lowly doped region. A new model that takes this effect into account as well as impact-ionization is presented.
  BibTeX:
  @article{Pan:TransED:2014,
  author = {Zhihao Pan and Schroeder and D. and Holland and S. and Krautschneider and W.H.},
  title = {{U}nderstanding and {M}odeling of {D}iode {V}oltage {O}vershoots {D}uring {F}ast {T}ransient {E}{S}{D} {E}vents},
  year = {2014},
  month = {08},
  journal = {IEEE Transactions on Electron Devices},
  number = {8},
  pages = {2682-2689},
  volume = {61} }
  [Abstract] [BibTeX] [DOI]
  
  
• M. Ziegler, D. Schroeder, W. Krautschneider, H. Kohlstedt
  Memristive operation mode of floating gate transistors for neuromorphic applications
  In Tagungsband "DPG-Frühjahrstagung" der Deutsche Physikalische Gesellschaft, 2014
  Dresden, 30. März - 4. April 2014
  Abstract:
  A memristive operation mode of a single floating gate transistor (MemFlash-cell) is presented. To ensure the memristive operation mode, the three-terminal device is reduced to a two-terminal device in such a way that the device resistance varied accordingly to the charge flow through the device during source-drain voltage application. In particular, we provide evidence that the MemFlash-cell can be used to mimic synaptic functionality. Furthermore, based on Hebbian learning, a synaptic analytical expression for the learning rate of this device is derived. The experimental findings are theoretically supported by a capacitive based model. The presented two-terminal MemFlash-cell can be considered as a potential substitute for any memristive device in neuromorphic circuits, cross bar arrays, or reconfigurable logics, and is compatible with state-of-the-art Si-fabrication technology.
  BibTeX:
  @inproceedings{Ziegler:DPG:2014,
  author = {M. Ziegler and D. Schroeder and W. Krautschneider and H. Kohlstedt},
  title = {{M}emristive operation mode of floating gate transistors for neuromorphic applications},
  year = {2014},
  month = {04},
  booktitle = {DPG-Fr{\"u}hjahrstagung},
  note = {Dresden, 30. M{\"a}rz - 4. April 2014},
  organization = {Deutsche Physikalische Gesellschaft} }
  [Abstract] [BibTeX]
  
  
• Kuhl, Matthias
  Full-custom Analog-mixed Signal Components for CMOS Integrated Autonomous Microelectronic Systems: Anwendungsbezogene Analog-mixed Signal Komponenten Für CMOS-integrierte Autonome Mikroelektronische Systeme
  Dissertation an der Universität, 2014
  Abstract:
  
  BibTeX:
  @phdthesis{kuhl2014full,
  author = {Kuhl and Matthias},
  title = {{F}ull-custom {A}nalog-mixed {S}ignal {C}omponents for {C}{M}{O}{S} {I}ntegrated {A}utonomous {M}icroelectronic {S}ystems: {A}nwendungsbezogene {A}nalog-mixed {S}ignal {K}omponenten {F}{\"u}r {C}{M}{O}{S}-integrierte {A}utonome {M}ikroelektronische {S}ysteme},
  year = {2014},
  school = {Universit{\"a}t} }
  [BibTeX]
  
  
• Kuhl, Matthias
  Full-Custom Analog/Mixed Signal Components for CMOS Integrated Autonomous Microelectronic Systems
  , 2014
  Abstract:
  
  BibTeX:
  @article{kuhlfull,
  author = {Kuhl and Matthias},
  title = {{F}ull-{C}ustom {A}nalog/{M}ixed {S}ignal {C}omponents for {C}{M}{O}{S} {I}ntegrated {A}utonomous {M}icroelectronic {S}ystems},
  year = {2014} }
  [BibTeX]
  
  
• Muller, Natalie and Manoli, Yiannos and Kuhl, Matthias
  A 1.6 nS, 16$mu$W, 30V Gm-C Integrator for Offset Voltage Monitoring in Neural Stimulators
  In Tagungsband "IEEE International Symposium on Circuits and Systems", 2014, p. 2381--2384
  Abstract:
  
  BibTeX:
  @inproceedings{muller20141,
  author = {Muller and Natalie and Manoli and Yiannos and Kuhl and Matthias},
  title = {{A} 1.6 n{S}, 16$mu${W}, 30{V} {G}m-{C} {I}ntegrator for {O}ffset {V}oltage {M}onitoring in {N}eural {S}timulators},
  year = {2014},
  booktitle = {IEEE International Symposium on Circuits and Systems},
  pages = {2381--2384} }
  [BibTeX]
  
  
• Mario A. Meza-Cuevas, Dietmar Schroeder, Wolfgang H. Krautschneider
  A scalable 64 channel neurostimulator based on a hybrid architecture of current steering DAC
  In Tagungsband "Middle East Conference on Biomedical Engineering (MECBME 2014)", 2014, p. 111-114
  Doha, Qatar, 17.-20.02.2014
  Abstract:
  In this work a 130 nm CMOS 64 channel neural stimulator is presented, which is scalable by connecting it in a daisy chain configuration,for applications requiring larger number of stimulation sites, as it is of interest for retinal implants with improved resolution. Each channel is composed of a hybrid architecture current steering 8 bit DAC, enabling the low power consumption and high channel integration on a small chip area. Besides, the DAC allows stimulating with several waveforms in order to save stimulation energy. An onchip module was implemented to control galvanostatic deposition of PEDOT on the electrodes. A schema is presented to avoid the residual charge due to cross electrode stimulation and process mismatch.
  BibTeX:
  @inproceedings{Meza:MECBME:2014,
  author = {Mario A. Meza-Cuevas and Dietmar Schroeder and Wolfgang H. Krautschneider},
  title = {{A} scalable 64 channel neurostimulator based on a hybrid architecture of current steering {D}{A}{C}},
  year = {2014},
  booktitle = {Middle East Conference on Biomedical Engineering (MECBME 2014)},
  note = {Doha, Qatar, 17.-20.02.2014},
  pages = {111-114} }
  [Abstract] [BibTeX] [DOI]
  
  

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