2007

• A. Weber, A. Birner, W. Krautschneider
  DRAM retention tail improvement by trap passivation
  Artikel in "Solid-State Electronics", vol. 51, p. 1534-1539, 2007
  Abstract:
  A very efficient method to reduce gate induced drain leakage (GIDL) as the dominant leakage path in the tail part of DRAM data retention time distribution is presented. Different to other reports, GIDL is addressed by trap passivation instead of lowering of electric fields. Stable passivation of traps is achieved by implantation of fluorine into S/D regions of 512 Mbit and 1 Gbit DRAMs in 110 nm technology. It was found that the position of the F-implant within the process flow plays a key role to enable trap reduction and retention tail improvement. Systematic implant experiments were carried out resulting in a failcount reduction of up to 40%. Detailed activation energy analysis on individual memory cells confirms the validity of the retention tail model and the selective reduction of GIDL traps by F-implantation.
  BibTeX:
  @article{Weber:tail:2007,
  author = {A. Weber and A. Birner and W. Krautschneider},
  title = {{D}{R}{A}{M} retention tail improvement by trap passivation},
  year = {2007},
  month = {11},
  journal = {Solid-State Electronics},
  pages = {1534-1539},
  volume = {51} }
  [Abstract] [BibTeX] [DOI]
  
  
• Andreas Domdey, Kristian Hafkemeyer, Dietmar Schröder, Wolfgang Krautschneider
  Automated system for simultaneous large-scale stress test of ultra-thin gate dielectrics to analyse reliability
  In Tagungsband "ProRISC2007 Workshop", 2007
  ProRISC
  Abstract:
  
  BibTeX:
  @inproceedings{Domdey:ProRISC:2007,
  author = {Andreas Domdey and Kristian Hafkemeyer and Dietmar Schr{\"o}der and Wolfgang Krautschneider},
  title = {{A}utomated system for simultaneous large-scale stress test of ultra-thin gate dielectrics to analyse reliability},
  year = {2007},
  month = {11},
  booktitle = {ProRISC2007 Workshop},
  note = {ProRISC} }
  [BibTeX]
  
  
• Kristian M. Hafkemeyer, Wjatscheslaw Galjan, Jakob M. Tomasik, Dietmar Schroeder, Wolfgang H. Krautschneider
  System-on-Chip Approach for Biomedical Signal Acquisition
  In Tagungsband "ProRISC2007 Workshop", 2007
  ProRISC2007
  Abstract:
  Abstract—A system-on-chip (SoC) approach for biomedical signal data acquisition in 0.35 μm 3.3 V CMOS technology is presented. The SoC is adaptable for multiple specific applications and is intended to be utilized in a low-power or a low-noise biomedical domain. A new approach for CMRR calibration technique has been used achieving a CMRR value larger than 80 dB at large DC-offsets.
  BibTeX:
  @inproceedings{Hafkemeyer:ProRISC:2007,
  author = {Kristian M. Hafkemeyer and Wjatscheslaw Galjan and Jakob M. Tomasik and Dietmar Schroeder and Wolfgang H. Krautschneider},
  title = {{S}ystem-on-{C}hip {A}pproach for {B}iomedical {S}ignal {A}cquisition},
  year = {2007},
  month = {11},
  booktitle = {ProRISC2007 Workshop},
  note = {ProRISC2007} }
  [Abstract] [BibTeX]
  
  
• D. Liebig, W. Krautschneider, K. Schünemann, K. Hafkemeyer, and A. Domdey
  First Principle Cellular Automata Simulation of Transport in Short Channel MOS-FET for Self-consistent Atomistic Modeling of Degradation in Ultra Thin Silicon-Dioxide Dielectrics
  In Tagungsband "SAFE 2007", 2007
  SAFE2007
  Abstract:
  Abstract—A new fully self-consistent cellular automata physical transport simulation is presented. In a numerically high efficient way semi-classical three dimensional and two dimensional lateral transport in quantized sub bands is calculated. The simulator accurately calculates output characteristics and gives insight into all relevant microscopic details of electron and hole transport by accurately calculating the distribution function solving the Boltzmann transport equation. By coupling the device simulator with atomistic molecular dynamics calculation of atom-reconfiguration in the SiO2 layer is achieved.
  BibTeX:
  @inproceedings{Liebig:MOS-FET:2007,
  author = {D. Liebig and W. Krautschneider and K. Sch{\"u}nemann and K. Hafkemeyer and and A. Domdey},
  title = {{F}irst {P}rinciple {C}ellular {A}utomata {S}imulation of {T}ransport in {S}hort {C}hannel {M}{O}{S}-{F}{E}{T} for {S}elf-consistent {A}tomistic {M}odeling of {D}egradation in {U}ltra {T}hin {S}ilicon-{D}ioxide {D}ielectrics},
  year = {2007},
  month = {11},
  booktitle = {SAFE 2007},
  note = {SAFE2007} }
  [Abstract] [BibTeX]
  
  
• P. Meier auf der Heide, C. Bronskowski, J.M. Tomasik, D. Schroeder
  A CMOS operational amplifier with constant 68° phase margin over its whole range of noise-power trade-off programmability
  In Tagungsband "33th European Solid-State Circuits Conference (ESSCIRC 2007)", 2007, p. 452-455, Herausgeber D. Schmitt-Landsiedel, T. Noll
  Munich, Germany, 11.-13. September 2007
  Abstract:
  The problem of variable phase margin of our programmable Operational Amplifier (OpAmp), which was presented at ESSCIRC 2006, has been solved. The OpAmp is programmable concerning noise and power consumption, while the phase margin is kept at an approximately constant value of 68° for the whole range of programmability. Experimental results for a 0.35 μm CMOS OpAmp show either low noise of 3.6 nV/sqrt(Hz) or low power consumption of 59 μW, and a phase margin variation of only 6°.
  BibTeX:
  @inproceedings{MadHeide:ESSCIRC:2007,
  author = {P. Meier auf der Heide and C. Bronskowski and J.M. Tomasik and D. Schroeder},
  title = {{A} {C}{M}{O}{S} operational amplifier with constant 68° phase margin over its whole range of noise-power trade-off programmability},
  year = {2007},
  month = {09},
  booktitle = {33th European Solid-State Circuits Conference (ESSCIRC 2007)},
  editor = {D. Schmitt-Landsiedel, T. Noll},
  note = {Munich, Germany, 11.-13. September 2007},
  pages = {452-455} }
  [Abstract] [BibTeX]
  
  
• W. von Emden, W. Krautschneider, G. Tempel, R. Hagenbeck and M.F. Beug
  A modified constant field charge pumping method for sensitive profiling of near-junction charges
  In Tagungsband "ESSDERC 2007", 2007
  Veldhofen/The Netherlands
  Abstract:
  Abstract—The functionality of nonvolatile memories with lateral multi-bit charge storage capabilities like NROM/ TwinFlash is critically related to spatial separation of the injected charge quantities to discriminate different logical states. In this paper we develop an adapted methodology to extract local charge densities based on the constant field charge pumping method. Our method overcomes the problem of non elf-consistency of conventional constant field charge pumping by determination of the spatial coordinate after every injection step. The method is demonstrated to directly extract the electron/ hole mismatch after program and erase injection.
  BibTeX:
  @inproceedings{vEmden:charges:2007,
  author = {W. von Emden and W. Krautschneider and G. Tempel and R. Hagenbeck and M.F. Beug},
  title = {{A} modified constant field charge pumping method for sensitive profiling of near-junction charges},
  year = {2007},
  month = {09},
  booktitle = {ESSDERC 2007},
  note = {Veldhofen/The Netherlands} }
  [Abstract] [BibTeX]
  
  
• Alexander Mora-Sánchez
  Sigma-Delta Analog-to-Digital Modulators with a Single Operational Transconductance Amplifier for Low-Power SoC Design in Biomedical Applications
  Dissertation an der TUHH, 2007
  Abstract:
  
  BibTeX:
  @phdthesis{Sigma:Mora:2007,
  author = {Alexander Mora-Sánchez},
  title = {{S}igma-{D}elta {A}nalog-to-{D}igital {M}odulators with a {S}ingle {O}perational {T}ransconductance {A}mplifier for {L}ow-{P}ower {S}o{C} {D}esign in {B}iomedical {A}pplications},
  year = {2007},
  month = {08},
  school = {TUHH} }
  [BibTeX]
  
  
• C. Bronskowski, D. Schroeder
  Systematic design of programmable operational amplifiers with noise–power trade-off
  Artikel in "IET Circuits, Devices & Systems", vol. 1, Nr. 1, p. 41--49, 2007
  Abstract:
  A methodology for the systematic design of a programmable operational amplifier (opamp) is described. With this methodology, the opamp is programmable concerning noise and power consumption while keeping the stability for the whole operation range with a constant phase margin of 70°. The theoretical model is developed with the help of the transfer characteristics of the opamp determining the degrees of freedom. Experimental results for a 0.35-mm CMOS opamp show either ultra low-noise of 2 nV/sqrt(Hz) or low-power consumption of 140 uW while keeping the opamp stable over the whole range of programmability.
  BibTeX:
  @article{Bronsk:2007,
  author = {C. Bronskowski and D. Schroeder},
  title = {{S}ystematic design of programmable operational amplifiers with noise–power trade-off},
  year = {2007},
  month = {01},
  journal = {IET Circuits, Devices {&} Systems},
  number = {1},
  pages = {41--49},
  volume = {1} }
  [Abstract] [BibTeX]
  
  
• A. Hanoun, H. Manteuffel, F. Mayer-Lindenberg, W. Galjan
  Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array
  Artikel in "Proc. IEEE Intern. Conf. on Signal Processing and Communication", p. 832-835, 2007
  Abstract:
  In this paper, we present the architecture of a coarsegrain reconfigurable cell designed for pipelined arithmetic computing applications. We apply the concept of separation between control-path and computation-path logic in the so-called reconfigurable coprocessor array architecture. Variations of the cells are implemented on CMOS 0.35 technology and subjected to a group of benchmarks. The resulting delay area products showed that double-ALU cells have about 50% smaller areadelay product than the single-ALU cell has.
  BibTeX:
  @article{Galjan:array:2007,
  author = {A. Hanoun and H. Manteuffel and F. Mayer-Lindenberg and W. Galjan},
  title = {{A}rchitecture of a pipelined datapath coarse-grain reconfigurable coprocessor array},
  year = {2007},
  journal = {Proc. IEEE Intern. Conf. on Signal Processing and Communication},
  pages = {832-835} }
  [Abstract] [BibTeX]
  
  
• Renato Rimolo-Donadio and Antonio J. Acosta and Wolfgang Krautschneider
  Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications
  Artikel in "ISCAS Conference", 2007
  Abstract:
  Abstract- This work proposes the usage of staggered initialization schemes in digital sequential circuits as complementary technique to reduce the simultaneous switching activity, pursuing the minimization of switching noise levels. Simultaneous switching noise (SSN) generation has been evaluated in digital sequential circuits during initialization and a general synthesis methodology has been proposed in order to implement the staggered initialization schemes at system level. The evaluation of this methodology was made with counter arrays using 0.35μm AMS library cells. In addition, timing considerations, clock suppression during initialization cycles, and the type of cell chosen to implement the staggered distribution are discussed. Main results include noise reduction levels, by suppression of power supply fluctuations, up to 66.7% in post-layout simulations when using staggered techniques enhanced with clock gating during initialization.
  BibTeX:
  @article{Rimolo-Donadio:ISCAS:2007,
  author = {Renato Rimolo-Donadio and Antonio J. Acosta and Wolfgang Krautschneider},
  title = {{A}synchronous {S}taggered {S}et/{R}eset {T}echniques for {L}ow-{N}oise {A}pplications},
  year = {2007},
  journal = {ISCAS Conference} }
  [Abstract] [BibTeX]
  
  
• Jakob M. Tomasik, Wjatscheslaw Galjan
  M3C: A Multi Monitoring Medical Chip for Homecare Applications
  Artikel in "Activity Report 2006, Europractice IC Service", 2007
  Abstract:
  
  BibTeX:
  @article{Europractice06,
  author = {Jakob M. Tomasik and Wjatscheslaw Galjan},
  title = {{M}3{C}: {A} {M}ulti {M}onitoring {M}edical {C}hip for {H}omecare {A}pplications},
  year = {2007},
  journal = {Activity Report 2006, Europractice IC Service} }
  [BibTeX]
  
  

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