2006

• Böscke, T., Govindarajan, S., Fachmann, C., Heitmann, J., Avellan, A., Schröder, U., Kudelka, S., Hirsch, P.D., Krug, C., Hung, P.Y., Song, S.C., Ju, B.S., Price, G., Pant, G., Gnade, B.E., Krautschneider, W., Lee, B.-H., Jammy, R.
  Tetragonal phase stabilization by doping as an enabler of thermally stable HfO2 based MIM and MIS capacitors for sub 50 nm deep trench DRAM
  In Tagungsband "International Electron Device Meeting", 2006
  IEDM, San Francisco
  Abstract:
  We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET <1.3 nm was achieved at the deep trench DRAM thermal budget of 1000°C.
  BibTeX:
  @inproceedings{B{\"o}scke:HfO2:2006,
  author = {B{\"o}scke and T. and Govindarajan and S. and Fachmann and C. and Heitmann and J. and Avellan and A. and Schr{\"o}der and U. and Kudelka and S. and Hirsch and P.D. and Krug and C. and Hung and P.Y. and Song and S.C. and Ju and B.S. and Price and G. and Pant and G. and Gnade and B.E. and Krautschneider and W. and Lee and B.-H. and Jammy and R.},
  title = {{T}etragonal phase stabilization by doping as an enabler of thermally stable {H}f{O}2 based {M}{I}{M} and {M}{I}{S} capacitors for sub 50 nm deep trench {D}{R}{A}{M}},
  year = {2006},
  month = {12},
  booktitle = {International Electron Device Meeting},
  note = {IEDM, San Francisco} }
  [Abstract] [BibTeX]
  
  
• A. Domdey, K. Hafkemeyer, T. Knudsen, W. Krautschneider
  First principles study of the degradation of silicon-dioxide gate dielectrics
  In Tagungsband "Proc. 9th Workshop on Semiconductor Advances for Future Electronics", 2006, Nr. 9
  SAFE2006
  Abstract:
  Abstract—A large-scale automated test system is presented that permits to analyse the gate dielectric degradation of thousands of MOS devices simultaneously. The system supports stress tests at elevated temperature and supply voltage as well as longterm tests. It aims at the creation of large and thus significant statistics about the degradation process as a function of time.
  BibTeX:
  @inproceedings{Domdey:gate:2006,
  author = {A. Domdey and K. Hafkemeyer and T. Knudsen and W. Krautschneider},
  title = {{F}irst principles study of the degradation of silicon-dioxide gate dielectrics},
  year = {2006},
  month = {11},
  booktitle = {Proc. 9th Workshop on Semiconductor Advances for Future Electronics},
  note = {SAFE2006},
  number = {9} }
  [Abstract] [BibTeX]
  
  
• Kristian Hafkemeyer, Andreas Domdey, Wolfgang H. Krautschneider
  Design of a process-parameter independent test-structure for reliability tests
  In Tagungsband "ProRISC2006 Workshop, Veldhoven (The Netherlands), 23.-24. November 2006", 2006
  ProRISC
  Abstract:
  A test-structure for statistical measurements of MOSFET failures caused by the time dependent eielectric breakdown with an external microcontroller is presented. The concept is technology independent and can be used to adjust and verify existing breakdown models.
  BibTeX:
  @inproceedings{RELTEST2006,
  author = {Kristian Hafkemeyer and Andreas Domdey and Wolfgang H. Krautschneider},
  title = {{D}esign of a process-parameter independent test-structure for reliability tests},
  year = {2006},
  month = {11},
  booktitle = {ProRISC2006 Workshop, Veldhoven (The Netherlands), 23.-24. November 2006},
  note = {ProRISC} }
  [Abstract] [BibTeX]
  
  
• Galjan, W. and Hanoun, A. and Krautschneider, W.H. and Mayer-Lindenberg, F.
  Distributed processor network on a single chip
  In Tagungsband "ProRISC2006 Workshop, Veldhoven (The Netherlands), 23.-24. November 2006", 2006
  ProRISC2006
  Abstract:
  Abstract—The Parallel-CPUs-On-Chip project aims at implementing a distributed computing architectures with scalable performance. As a proof of concept, we integrated two 16-bit sequential microprocessors called CPU-III on a chip. The CPU-III supports many vital features for controlling including multi-threading, two-stage execution pipelining and an enhanced coprocessor interface which also supports multi-threading and coprocessor pipelining.
  BibTeX:
  @inproceedings{Galjan:chip:2006,
  author = {Galjan and W. and Hanoun and A. and Krautschneider and W.H. and Mayer-Lindenberg and F.},
  title = {{D}istributed processor network on a single chip},
  year = {2006},
  month = {11},
  booktitle = {ProRISC2006 Workshop, Veldhoven (The Netherlands), 23.-24. November 2006},
  note = {ProRISC2006} }
  [Abstract] [BibTeX]
  
  
• Rimolo-Donadio, R. and Mora-Sanchez, A. and Schroeder, D.
  High slew rate configurabel class AB fully differential operational transconductance amplifier for switched capacitor circuit applications
  In Tagungsband "ProRisc2006 Workshop, Veldhoven (The Netherlands), 23.-24. November 2006", 2006
  ProRisc Veldhoven 23.-24. November 2006
  Abstract:
  Abstract—In this paper, a configurable dynamically-biased class AB operational transconductance amplifier (OTA) for switched-capacitor (SC) circuit applications, based on the utilization of the flipped voltage follower (FVF), is presented. The proposed OTA offers high slew rate, low power consumption, and its speed can be configured to work in a unitary-gain bandwidth (UGBW) range from about 2MHz up to 50MHz. The amplifier has been designed to operate at 3.3V using a 0.35um CMOS technology. Post-layout simulation results show that the OTA is suitable for the design of low-power and high-slew rate SC circuit applications, offering better performance in those aspects with respect to classical OTA architectures.
  BibTeX:
  @inproceedings{Rimolo:slew:2006,
  author = {Rimolo-Donadio and R. and Mora-Sanchez and A. and Schroeder and D.},
  title = {{H}igh slew rate configurabel class {A}{B} fully differential operational transconductance amplifier for switched capacitor circuit applications},
  year = {2006},
  month = {11},
  booktitle = {ProRisc2006 Workshop, Veldhoven (The Netherlands), 23.-24. November 2006},
  note = {ProRisc Veldhoven 23.-24. November 2006} }
  [Abstract] [BibTeX]
  
  
• Carsten Bronskowski, Dietmar Schroeder
  An ultra low-noise CMOS operational amplifier with programmable noise-power trade-off
  In Tagungsband "32th European Solid-State Circuits Conference (ESSCIRC 2006)", 2006, p. 368-371, Herausgeber C. Enz, M. Declercq, Y. Leblebici
  Montreux, Switzerland, 19.-21. September 2006
  Abstract:
  A programmable operational amplifier (OpAmp) concerning noise and power consumption is described. Key design issues for achieving programmability of a preselected OpAmp architecture are discussed. Experimental results for a 0.35 um CMOS OpAmp show either ultra low noise of 2 nV/sqrt(Hz) or low power consumption of 140 uW. The OpAmp remains stable over the whole range of programmability.
  BibTeX:
  @inproceedings{Bronskowski:ESSCIRC:2006,
  author = {Carsten Bronskowski and Dietmar Schroeder},
  title = {{A}n ultra low-noise {C}{M}{O}{S} operational amplifier with programmable noise-power trade-off},
  year = {2006},
  month = {09},
  booktitle = {32th European Solid-State Circuits Conference (ESSCIRC 2006)},
  editor = {C. Enz, M. Declercq, Y. Leblebici},
  note = {Montreux, Switzerland, 19.-21. September 2006},
  pages = {368-371} }
  [Abstract] [BibTeX]
  
  
• Alexander Mora-Sanchez, Dietmar Schroeder, Wolfgang H. Krautschneider
  A 3rd-order single-OTA Sigma-Delta modulator for low-power mixed-signal system-on-chip applications
  In Tagungsband "ANALOG 2006", Verlag VDE-Verlag, 2006, vol. 196, Serie "ITG-Fachbericht", p. 21--26
  9. ITG/GMM-Fachtagung, Dresden, 27.-29. September 2006
  Abstract:
  This paper brings forward a 3rd-order single operational transconductance amplifier (OTA) sigma-delta analogue-to-digital (A/D) modulator as a means to achieve low-power A/D conversion on mixed-signal system-on-chip (SoC) designs. The proposed concept is based on the utilisation of a single OTA within the modulator structure which is shared in time in order to perform concurrently sampling and integration. Thus, power consumption as well as on-chip area can be saved since only one OTA is used. The paper also discusses the impact of nonidealities (e.g. finite gain and bandwidth of the OTA, noise folding, switch on-resistance, etc.) on the performance of the proposed modulator. A prototype of the 3rd-order modulator based on a 0.35 μm CMOS technology is presented in order to prove the correctness of the proposed concept.
  BibTeX:
  @inproceedings{Mora:OTA:2006,
  author = {Alexander Mora-Sanchez and Dietmar Schroeder and Wolfgang H. Krautschneider},
  title = {{A} 3rd-order single-{O}{T}{A} {S}igma-{D}elta modulator for low-power mixed-signal system-on-chip applications},
  year = {2006},
  month = {09},
  booktitle = {ANALOG 2006},
  note = {9. ITG/GMM-Fachtagung, Dresden, 27.-29. September 2006},
  pages = {21--26},
  publisher = {VDE-Verlag},
  series = {ITG-Fachbericht},
  volume = {196} }
  [Abstract] [BibTeX]
  
  
• N. Van Helleputte, A. Mora-Sanchez, W. Galjan, J. M. Tomasik, D. Schroeder, W. H. Krautschneider and R. Puers
  A flexible system-on-chip (SoC) for biomedical signal acquisition and processing
  In Tagungsband "EUROSENSORS XX", 2006
  Goeteborg, Sweden, 17th-20th September 2006
  Abstract:
  In this paper a system-on-chip (SoC) that combines multiple biomedical signal acquisition (ECG, EEG, EP and respiration-related signals) with on-chip digital signal processing is presented. The embedded flexibility of the SoC facilitates its use in a multitude of applications. Time-sharing of the operational transconductance amplifier within the analog-to-digital converters is employed in order to lower the power consumption and to save area. Built-in self-test (BIST) and autocalibration capabilities are included to enhance its reliability. The low noise analog front end is fully programmable to achieve the best power-noise trade-off for the application at hand. A prototype has been manufactured in 0.35μm 3.3 V CMOS technology.
  BibTeX:
  @inproceedings{Eurosens:2006,
  author = {N. Van Helleputte and A. Mora-Sanchez and W. Galjan and J. M. Tomasik and D. Schroeder and W. H. Krautschneider and R. Puers},
  title = {{A} flexible system-on-chip ({S}o{C}) for biomedical signal acquisition and processing},
  year = {2006},
  month = {09},
  booktitle = {EUROSENSORS XX},
  note = {Goeteborg, Sweden, 17th-20th September 2006} }
  [Abstract] [BibTeX]
  
  
• Galjan, W. and Hanoun, A. and Krautschneider, W.H. and Mayer-Lindenberg, F.
  Architectures for system-on-chip computation units
  In Tagungsband "Kleinheubacher Tagung", 2006
  Kleinheubacher Tagung
  Abstract:
  The trend for minimizing system sizes and reducing the power consumption results in demand for Application Specific Integrated Circuits (ASICs). Especially biomedical applications with implantable devices are critical for these system parameters. As biomedical signals have almost an analog character, digitalizing and after that applying filtering algorithms is the usual procedure for signal acquisition systems. For this application field two different strategies of digital computation units have been pursued. The first architecture, it was implemented and manufactured in 0.35μm CMOS technology, consists of a powerful 16-bit fix-point DSP with 17kB on chip memory. This DSP, which is licensed IP-Core (Evatronix) written in Verilog, supports one-cycle MAC-instructions and has eight auxiliary registers for different addressing modes, allowing signal filtering of more than ten 16-bit ADC-channels sequentially. To comply with very strong power consumption limitations the digital unit is able to reduce the clock frequency for every system block and also its own. This scaling of computation power and of the resolution of ADC-chains allows to use this SoC for different biological signals. The idea for the second implementation is to allow parallelized computation and to divide the whole system in small clusters. Therefore an architecture was developed, which allows to connect together through a parallel bus a maximum of 8 CPUs. For testing purpose an ASIC was implemented consisting mainly of two identical 16-bit micro-CPUs, which are connected together through a parallel bus. Both threads, running on the both CPUs, execute independent tasks but share the same coprocessor that typically supplies some complex application specific operations. The coprocessor interface strongly supports configurable pipelining, which enforces the stepwise controlling of computations on the coprocessor. Because the design of applicationspecific computation units can be reduced to a design of only one coprocessor, this system is flexible and scalable to different applications.
  BibTeX:
  @inproceedings{Galjan:units:2006,
  author = {Galjan and W. and Hanoun and A. and Krautschneider and W.H. and Mayer-Lindenberg and F.},
  title = {{A}rchitectures for system-on-chip computation units},
  year = {2006},
  month = {09},
  booktitle = {Kleinheubacher Tagung},
  note = {Kleinheubacher Tagung} }
  [Abstract] [BibTeX]
  
  
• Tomasik, J.M., Krautschneider, W.H.
  Review of 1/f noise in MOSFETs and development of an experimental opamp using switched biasing to reduce 1/f noise
  In Tagungsband "Kleinheubacher Tagung", 2006
  Kleinheubacher Tagung
  Abstract:
  1/f noise in metal-oxide-semiconductor field-effect transistors has been investigated for more than 40 years, still the theory is developed further to allow a better understanding of the underlying noise process. In particular, the question of how 1/f noise will scale with smaller technologies is a controversy topic. Two distinct explanations of 1/f noise emerged at the beginning of the investigation, the ΔN model that correlates the noise to fluctuations in the number of charge carriers and the Δμ model that correlates the noise to mobility fluctuations. These two models were merged together by Hung et al. in the unified 1/f noise model resulting in the dependency of the drain current fluctuation ΔI as a function of both ΔN and Δμ. Despite this outstanding model that is used in modern circuit simulation models like BSIM, there is still an extensive research in 1/f noise in MOSFETs raising new questions. An example is the effect of switching a MOSFET periodically from accumulation to inversion discovered by Bloom and Nemirovsky. This technique allows a physically based reduction of 1/f noise and the effect cannot be derived from the above models. An extensive research on this topic has been started by the publication of Gierkink et al. To exploit the switched bias effect in an analog circuit we developed an experimental opamp in CMOS 0.35μm technology using this technique. For this purpose we altered a regular opamp design already designed to be very low-noise. Measurements showed that the noise power could be reduced by a factor of 1.6 by switching some of the opamp’s MOSFETs periodically from accumulation to inversion.
  BibTeX:
  @inproceedings{Tomasik:1durchf:2006,
  author = {Tomasik and J.M. and Krautschneider and W.H.},
  title = {{R}eview of 1/f noise in {M}{O}{S}{F}{E}{T}s and development of an experimental opamp using switched biasing to reduce 1/f noise},
  year = {2006},
  month = {09},
  booktitle = {Kleinheubacher Tagung},
  note = {Kleinheubacher Tagung} }
  [Abstract] [BibTeX]
  
  
• Böscke, T. and Kudelka, A. and Sänger, A. and Müller, J. and Krautschneider, W.H.
  Investigation of the high temperature stability of TiN-Al203-TiN capacitiors for sub 50 nm deep trench DRAM
  In Tagungsband "Proc. 36th European Solid-State Device Research Conference (ESSDERC 2006)", 2006
  ESSDERC 2006, Montreux
  Abstract:
  Abstract—This paper deals with the investigation of mechanisms leading to a degradation of the electrical properties of titanium nitride - aluminum oxide - titanium nitride capacitors at high temperatures. Several degradation mechanisms could be identified by thorough electrical and physical characterization. The findings will serve as a future guide to build thermally stable MIM capacitors.
  BibTeX:
  @inproceedings{B{\"o}scke:TiN:2006,
  author = {B{\"o}scke and T. and Kudelka and A. and S{\"a}nger and A. and M{\"u}ller and J. and Krautschneider and W.H.},
  title = {{I}nvestigation of the high temperature stability of {T}i{N}-{A}l203-{T}i{N} capacitiors for sub 50 nm deep trench {D}{R}{A}{M}},
  year = {2006},
  month = {09},
  booktitle = {Proc. 36th European Solid-State Device Research Conference (ESSDERC 2006)},
  note = {ESSDERC 2006, Montreux} }
  [Abstract] [BibTeX]
  
  
• Weber, A and Birner, A. and Krautschneider, W.
  Retention tail improvement for 1 GBit DRAMs through trap passivation confirmed by activation energy analysis
  In Tagungsband "Proc. 36th European Solid-State Device Research Conference (ESSDERC 2006)", 2006, p. 185
  ESSDERC 2006, Montreux
  Abstract:
  Abstract— A very efficient method to reduce gate induced drain leakage (GIDL) as the dominant leakage path in the tail part of DRAM data retention time distribution is presented. Different to other reports, GIDL is addressed by trap passivation instead of lowering of electric fields. Stable passivation of traps is achieved by implantation of fluorine into S/D regions of 512Mbit and 1Gbit DRAMs in 110 nm technology. It was found that the position of the F-implant within the process flow plays a key role to enable trap reduction and retention tail improvement. Systematic implant experiments were carried out resulting in a failcount reduction of up to 40 %. Detailed activation energy analysis on individual memory cells confirms the validity of the retention tail model and the selective reduction of GIDL traps by fluorine implantation.
  BibTeX:
  @inproceedings{Krautschneider:DRAM:2006,
  author = {Weber and A and Birner and A. and Krautschneider and W.},
  title = {{R}etention tail improvement for 1 {G}{B}it {D}{R}{A}{M}s through trap passivation confirmed by activation energy analysis},
  year = {2006},
  month = {09},
  booktitle = {Proc. 36th European Solid-State Device Research Conference (ESSDERC 2006)},
  note = {ESSDERC 2006, Montreux},
  pages = {185} }
  [Abstract] [BibTeX]
  
  
• Paola Vega-Castillo
  Potentials and constraints of single-poly non-volatile memories
  Dissertation an der TU Hamburg-Harburg, Dissertation (Shaker Verlag Aachen), 2006
  Abstract:
  
  BibTeX:
  @phdthesis{Vega-Diss-2006,
  author = {Paola Vega-Castillo},
  title = {{P}otentials and constraints of single-poly non-volatile memories},
  year = {2006},
  month = {08},
  address = {Shaker Verlag Aachen},
  school = {TU Hamburg-Harburg},
  type = {Dissertation} }
  [BibTeX]
  
  
• Carsten Bronskowski
  Programmierbarer Operationsverstärker zur Erfassung von bioelektrischen Signalen mit unterschiedlichen Rausch- und Verlustleistungs-Anforderungen
  Dissertation an der TU Hamburg-Harburg (Shaker Verlag Aachen), 2006
  Abstract:
  In der vorliegenden Arbeit wird ein einstellbares Analoges Front End (AFE) vorgestellt, welches in einem integrierten Schaltkreis (ASIC) vorliegt. Das Analoge Front End erlaubt die Anpassung des ASICs an die jeweilige Spezifikation von EKG-, EEG-, EP- und EMG-Messgeräten und findet darüber hinaus in mobilen Messgerät-Einheiten Anwendung. Es besteht aus einem Vorverstärker, einem Nachverstärker, einem Tiefpass und einem Symmetrierverstärker. Hierbei sind die Spezifikations-Parameter Rauschen, Leistungsaufnahme, Verstärkung und Grenzfrequenz veränderbar. Die Realisierung der Einstellbarkeit des Analogen Front Ends hinsichtlich des Rauschens und der Leistungsaufnahme wird erst möglich durch die Verwendung von einstellbaren Operationsverstärkern, welche sich im Vorverstärker und im Nachverstärker des AFEs befinden. Hierzu wird in der vorliegenden Arbeit ein Konzept zum systematischen Entwurf eines einstellbaren Operationsverstärkers anhand von frei wählbaren Schaltungsparametern vorgestellt. Es konnte so ein Operationsverstärker realisiert werden, der über einen Steuerstrom variabel einstellbar bezüglich seines Rauschens und seiner Leistungsaufnahme ist.
  BibTeX:
  @phdthesis{Bronsko:Diss:2006,
  author = {Carsten Bronskowski},
  title = {{P}rogrammierbarer {O}perationsverst{\"a}rker zur {E}rfassung von bioelektrischen {S}ignalen mit unterschiedlichen {R}ausch- und {V}erlustleistungs-{A}nforderungen},
  year = {2006},
  month = {07},
  address = {Shaker Verlag Aachen},
  school = {TU Hamburg-Harburg} }
  [Abstract] [BibTeX]
  
  
• Weber, A and Birner, A. and Krautschneider, W.
  Method of activation energy analysis and application to individual cells of 256 Mb DRAM in 110 nm technology
  Artikel in "Solid-State-Electronics", p. 613, 2006
  Abstract:
  In DRAM every memory cell experiences an individual mixture of leakage currents which consume part of the stored charge and lead to a wide distribution of data retention time (tRet). This distribution consists of an intrinsic (main) and an extrinsic (tail) branch. The formalism of activation energies (Ea) provides information about the mechanisms involved. Activation energies of single cells in a 256M DDR memory chip and their dependence on negative gate bias (VNWLL) as well as body bias (VBB) have been investigated intensively for the first time. The worst tail cells – all within a small retention time interval – show a twofold and wide distribution of activation energies. The lower Ea distribution can be altered with VNWLL, whereas the higher Ea distribution only alters with VBB. Going from tail towards main distribution, the percentage of cells belonging to the low Ea part continuously decreases and finally disappears. We therefore conclude that a gate induced mechanism (GIDL) is the main component responsible for DRAM retention tail.
  BibTeX:
  @article{Krautschneider:256Mb:2006,
  author = {Weber and A and Birner and A. and Krautschneider and W.},
  title = {{M}ethod of activation energy analysis and application to individual cells of 256 {M}b {D}{R}{A}{M} in 110 nm technology},
  year = {2006},
  month = {04},
  journal = {Solid-State-Electronics},
  pages = {613} }
  [Abstract] [BibTeX]
  
  
• Vega-Castillo, P. and Krautschneider, W.H.
  Low Voltage, Low Power, Self-Clocked Single Poly CMOS Compatible OTP Memory System
  In Tagungsband "Proc. XII Workshop Iberchip", 2006
  Workshop Iberchip
  Abstract:
  1 ABSTRACT: A single poly non-volatile memory system for low voltage, low power analog calibration applications is presented, which performs the read, program and verify operations for a single-poly non-volatile memory. The reading circuitry performs single-ended sensing, thus no dummy cells are required. Furthermore, the system addresses the cells sequentially and automatically, is self-clocked and the operation frequency is adjustable. The system was fabricated using 0.35μm technology (nominal voltage of 3.3V). It operates down to 0.95V with a power consumption of 600nW during the reading operation. The timing unit operates down to 0.55V.
  BibTeX:
  @inproceedings{Vega-Castillo:Memory:2006,
  author = {Vega-Castillo and P. and Krautschneider and W.H.},
  title = {{L}ow {V}oltage, {L}ow {P}ower, {S}elf-{C}locked {S}ingle {P}oly {C}{M}{O}{S} {C}ompatible {O}{T}{P} {M}emory {S}ystem},
  year = {2006},
  month = {03},
  booktitle = {Proc. XII Workshop Iberchip},
  note = {Workshop Iberchip} }
  [Abstract] [BibTeX]
  
  
• Pereira-Arroyo, R. and Alvarado-Moya, P. and Krautschneider, W.H.
  Multi-objective optimization of MCML circuits using a genetic algorithm
  In Tagungsband "Proc. XII. Workshop Iberchip", 2006, p. 134
  San Jose, Costa Rica
  Abstract:
  This paper introduces the Pareto front as a useful analysis tool to explore the design space of MOS Current Mode Logic (MCML) circuits. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. As an example of the flexibility of this design automation approach, the results for an optimized fundamental inverter logic gate are presented. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task.
  BibTeX:
  @inproceedings{Krautschneider:MCML:2006,
  author = {Pereira-Arroyo and R. and Alvarado-Moya and P. and Krautschneider and W.H.},
  title = {{M}ulti-objective optimization of {M}{C}{M}{L} circuits using a genetic algorithm},
  year = {2006},
  month = {03},
  booktitle = {Proc. XII. Workshop Iberchip},
  note = {San Jose, Costa Rica},
  pages = {134} }
  [Abstract] [BibTeX]
  
  
• Vega-Castillo, P. and Krautschneider, W.H.
  Optimization and constraints of single-poly non-volatile memory cells for embedded applications
  In Tagungsband "Proc. XII. Workshop Iberchip", 2006, p. 120
  San Jose, Costa Rica
  Abstract:
  The influence of the cell geometry in the programming and erasing characteristics of a fully CMOS compatible singlepoly non-volatile memory cell for low cost embedded applications was investigated using cells fabricated in a standard CMOS 0.35μm-technology with transistor sizes varying form 10μm/0.3μm to 0.7μm/0.3μm, being the 0.7μm-wide cells the smallest single poly non-volatile memory cells reported until now. In addition to this, the impact of transistor separation is presented and discussed, together with the impact of the cell dimensions in the characteristics and endurance of the cells.
  BibTeX:
  @inproceedings{Vega:single-poly:2006,
  author = {Vega-Castillo and P. and Krautschneider and W.H.},
  title = {{O}ptimization and constraints of single-poly non-volatile memory cells for embedded applications},
  year = {2006},
  month = {03},
  booktitle = {Proc. XII. Workshop Iberchip},
  note = {San Jose, Costa Rica},
  pages = {120} }
  [Abstract] [BibTeX]
  
  
• Alexander Mora-Sanchez, Dietmar Schroeder, Wolfgang H. Krautschneider
  Preliminaries on low-power analog-to-digital conversion for system-on-chip design: sigma-delta modulator with a single amplifier and a novel 14-transistor 1-bit full adder
  In Tagungsband "XII Iberchip Workshop IWS-2006", 2006
  Konferenz San Jose (Costa Rica), 22-24 März 2006
  Abstract:
  Two approaches for low-power analog-to-digital (A/D) conversion for biomedical-oriented System-on-Chip (SoC) design are addressed in this paper. The first approach introduces the use of a single amplifier to realize switchedcapacitor- based 1-bit low-pass A/D sigma-delta modulators, thus reducing the power consumption of the modulator compared to the traditional counterpart (approx. 50% and 25% in 2nd- and 3rd-order modulation, respectively). Here, the single amplifier is time-shared to perform sampling and integration operations concurrently. The second approach introduces a novel small-area low-power 1-bit CMOS-based full adder cell to be used in the digital signal processing part of the SoC, which includes the digital filters of the sigma-delta A/D converters. The novel full adder comprises only 14 transistors. Compared to the standard 28-transistor full adder found in the standard library cell of the 0.35 μm 3.30 V CMOS technology used in this work, it consumes 45% less power and occupies 47% less area.
  BibTeX:
  @inproceedings{Mora:lowpowerADC:2006,
  author = {Alexander Mora-Sanchez and Dietmar Schroeder and Wolfgang H. Krautschneider},
  title = {{P}reliminaries on low-power analog-to-digital conversion for system-on-chip design: sigma-delta modulator with a single amplifier and a novel 14-transistor 1-bit full adder},
  year = {2006},
  month = {03},
  booktitle = {XII Iberchip Workshop IWS-2006},
  note = {Konferenz San Jose (Costa Rica), 22-24 M{\"a}rz 2006} }
  [Abstract] [BibTeX]
  
  
• Kristian Hafkemeyer, Alexander Mora-Sanchez, Dietmar Schroeder
  Low-Power Processing of ECG-Signals Using Predictive A/D-Conversion
  In Tagungsband "XII Workshop Iberchip", 2006, p. 162-165
  Konferenz San Jose (Costa Rica), 22-24 März 2006
  Abstract:
  A predictive A/D-converter for the acquisition and digitisation of electrocardiographic (ECG) signals is presented. The proposed converter is intended to be utilised in lowpower ECG applications and has several advantages contrary to an conventional ECG channel or former predictive signal processing concepts. The system works as an closed loop encoder, runs at decreased power consumption and is fully integratable on chip. The theoretical approach is deduced here in detail and the results are proven with simulations and measurements on prototyped circuits.
  BibTeX:
  @inproceedings{PRED06,
  author = {Kristian Hafkemeyer and Alexander Mora-Sanchez and Dietmar Schroeder},
  title = {{L}ow-{P}ower {P}rocessing of {E}{C}{G}-{S}ignals {U}sing {P}redictive {A}/{D}-{C}onversion},
  year = {2006},
  month = {03},
  booktitle = {XII Workshop Iberchip},
  note = {Konferenz San Jose (Costa Rica), 22-24 M{\"a}rz 2006},
  pages = {162-165} }
  [Abstract] [BibTeX]
  
  
• R. Meixner, R. Wille, P. Schertling, H. Goebel, H. Harde, K.-H. Steglich, F.A. Yildirim, W. Bauhofer, W. Krautschneider
  Bottom gate organic field effect transistors made by laser structuring
  Artikel in "Elsevier Organic Electronic", vol. 7, p. 586-591, 2006
  Abstract:
  This paper presents a process to manufacture all-polymer field effect transistors in a bottom gate configuration where all electrodes - including the gate electrode - are patterned using an excimer laser in combination with a scanning unit. This technique yields channel length of 10 µm between the source and the drain electrodes. Being a combination of a scanning and a single shot patterning process it is a promising candidate for an industrial process with a resolution of 10 µm and an operational throughput of at least 6 cm²/s.
  BibTeX:
  @article{meixner:yildrin:2006,
  author = {R. Meixner and R. Wille and P. Schertling and H. Goebel and H. Harde and K.-H. Steglich and F.A. Yildirim and W. Bauhofer and W. Krautschneider},
  title = {{B}ottom gate organic field effect transistors made by laser structuring},
  year = {2006},
  journal = {Elsevier Organic Electronic},
  pages = {586-591},
  volume = {7} }
  [Abstract] [BibTeX]
  
  
• Faruk Altan Yildirim, Ronald Meixner, Robert Roman Schliewe, Wolfgang Bauhofer, Holger Goebel, Wolfgang Krautschneider
  Polymer Gate Dielectrics for High Performance Organic Field-Effect Transistors
  Artikel in "Mater.Res.Soc.Symp.Proc.", vol. 937, 2006
  Abstract:
  Solution-processed bottom-gate organic field-effect transistors (OFETs) with different polymeric dielectric materials were produced and characterized. As the active semiconductor layer, regioregular poly(3-hexylthiophene) (rr-P3HT) was used. Dielectric materials of high chemical stability with simple processing conditions were used as gate-insulation in OFETs. Also, the dielectric properties of the polymeric layers were investigated in metal-insulator-metal capacitor structures, where the thicknesses of the films were exactly the same as they were in the OFETs. The specific volume resistivity and dielectric constant values determined were then used to explain the electrical behavior of OFETs. The devices having BCB, SU-8 and NOA74 as dielectric layers exhibited the desired transistor characteristics, whereas the transistors with Avatrel dielectric did not, due to higher gate-leakages. As a result, SU-8 and NOA74 resins were proven to be good candidates for gate-dielectric usage in solution-processed all-polymer OFETs.
  BibTeX:
  @article{Krautschneider:Gate:2006,
  author = {Faruk Altan Yildirim and Ronald Meixner and Robert Roman Schliewe and Wolfgang Bauhofer and Holger Goebel and Wolfgang Krautschneider},
  title = {{P}olymer {G}ate {D}ielectrics for {H}igh {P}erformance {O}rganic {F}ield-{E}ffect {T}ransistors},
  year = {2006},
  journal = {Mater.Res.Soc.Symp.Proc.},
  volume = {937} }
  [Abstract] [BibTeX]
  
  
• R.R. Schliewe, F.A. Yildirim, W. von Emden, R. Witte, W. Bauhofer, W. Krautschneider
  Static model for organic field-effect transistors including both gate-voltage-dependent mobility and depletion effect
  Artikel in "Applied Physics Letters", vol. 88, p. 233514-1-3, 2006
  Abstract:
  Physics-based models of organic field-effect transistors
  OFETs which can be used for computer-aided simulation of organic integrated circuits were investigated. For this purpose hybrid OFETs with poly
  3-hexylthiophene-2,5-diyl as the semiconductor were fabricated and characterized. The differential drain-source resistance reveals the need for a unified consideration of a gate-voltage-dependent mobility and of the depletion effect. We avoid neglecting the capacitance of the insulator and the semiconductor which would have otherwise introduced restrictions. The analytic modeling yields a compact static equivalent circuit diagram.
  BibTeX:
  @article{Krautschneider:model:2006,
  author = {R.R. Schliewe and F.A. Yildirim and W. von Emden and R. Witte and W. Bauhofer and W. Krautschneider},
  title = {{S}tatic model for organic field-effect transistors including both gate-voltage-dependent mobility and depletion effect},
  year = {2006},
  journal = {Applied Physics Letters},
  pages = {233514-1-3},
  volume = {88} }
  [Abstract] [BibTeX]
  
  
• R.M. Meixner, H. Göbel, F.A. Yildirim, W. Bauhofer, W. Krautschneider
  Wavelength-selective organic field-effect phototransistors based on dye-doped poly-3-hexylthiophene
  Artikel in "Applied Physics Letters", vol. 89, p. 092110-1-3, 2006
  Abstract:
  The authors present a strategy to manufacture wavelength-selective field-effect phototransistors by employing dye-doped poly-3-hexylthiophene
  P3HT as a semiconducting layer. The dye doping of the semiconductor P3HT was achieved by blending organic molecules—coumarin 6, oxazine 1, and nile red—into the conjugated organic polymer. Illuminating these transistors with monochromatic light in the range of 400–700 nm resulted in varying conductivities for certain wavelengths in dependence on the particular dye. This effect is attributed to the photogeneration of excitons on the dye molecules, which are subsequently transferred to the conjugated polymer.
  BibTeX:
  @article{Krautschneider:poly3:2006,
  author = {R.M. Meixner and H. G{\"o}bel and F.A. Yildirim and W. Bauhofer and W. Krautschneider},
  title = {{W}avelength-selective organic field-effect phototransistors based on dye-doped poly-3-hexylthiophene},
  year = {2006},
  journal = {Applied Physics Letters},
  pages = {092110-1-3},
  volume = {89} }
  [Abstract] [BibTeX]
  
  

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