2003

• Paola Vega-Castillo
  Los retos del bajo voltaje en memorias RAM
  Artikel in "TeraBit", Nr. vol 2, p. pp 8-11, 2003
  Abstract:
  Lower power dissipation requirements lead to lower supply voltages in RAM memories. However, this degrades the sensing speed. In this article, the basics of DRAM and SRAM sensing and the issues arising from lower supply voltages are presented. Countermeasures adopted by the designers to increase the memory performance under these conditions are summarized. The basics of current sensing for high speed, low voltage SRAMs are explained and discussed.
  BibTeX:
  @article{Vega-Castillo:memoriasRAM,
  author = {Paola Vega-Castillo},
  title = {{L}os retos del bajo voltaje en memorias {R}{A}{M}},
  year = {2003},
  month = {12},
  journal = {TeraBit},
  number = {vol 2},
  pages = {pp 8-11} }
  [Abstract] [BibTeX]
  
  
• R.R. Schliewe, F.A. Yildrim, W. Bauhofer, W. Krautschneider
  Electrode structures for characterization of organic materials and for application in organic electronics
  In Tagungsband "Proc. 6th Annual Workshop on Future Electronics SAFE", 2003
  Eindhoven, The Netherlands
  Abstract:
  We focussed on lateral electrode structures for the characterization of semiconducting polymers in the FET-arrangement. As test vehicles we used polymeric field-effect transistors that can be structured by laser writing. We also worked on fabrication of vertical structures of all-polymeric electrodes. They are promising candidates for all-polymer electronics.
  BibTeX:
  @inproceedings{Schliewe:SAFE:03,
  author = {R.R. Schliewe and F.A. Yildrim and W. Bauhofer and W. Krautschneider},
  title = {{E}lectrode structures for characterization of organic materials and for application in organic electronics},
  year = {2003},
  month = {11},
  booktitle = {Proc. 6th Annual Workshop on Future Electronics SAFE},
  note = {Eindhoven, The Netherlands} }
  [Abstract] [BibTeX]
  
  
• P. Vega-Castillo, S. Dhar, W.H. Krautschneider
  Non volatile memory cell for standard CMOS processes: A circuit-level simulation model
  In Tagungsband "Proc. 6th Annual Workshop on Future Electronics SAFE, Eindhoven, The Netherlands", 2003
  SAFE, Eindhoven
  Abstract:
  A model describing the programming operation of a single poly non-volatile memory cell was implemented in AHDL. The model, incorporated into a standard circuit-level simulator, enables fast and flexible simulation of the cell programming. Also, results from circuit-level and device-level simulations have been compared.
  BibTeX:
  @inproceedings{Vega-Safe-03,
  author = {P. Vega-Castillo and S. Dhar and W.H. Krautschneider},
  title = {{N}on volatile memory cell for standard {C}{M}{O}{S} processes: {A} circuit-level simulation model},
  year = {2003},
  month = {11},
  booktitle = {Proc. 6th Annual Workshop on Future Electronics SAFE, Eindhoven, The Netherlands},
  note = {SAFE, Eindhoven} }
  [Abstract] [BibTeX]
  
  
• A. Seekamp, A. Avellán, S. Schwantes, W. Krautschneider
  Simple estimation of the effect of hot-carrier degradation on scaled nMOSFETs
  Artikel in "International Journal of Electronics", vol. 90, Nr. 10, p. 607-12, 2003
  Abstract:
  The influence of parasitic charge at the Si-SiO2 interface on the characteristics of n-channel metal oxide semiconductor field effect transistors (nMOSFETs) scaled down to a feature size of 25nm is studied. Results are that the impact of parasitic charge on threshold voltage and drain current degradation significantly decreases. Additionally, as the hot-electron injection current densities are lowered for scaled-down nMOS transistors, less charge build-up occurs. This opens the perspective to make use of alternative gate dielectrics even if they have a higher interface trap density. These materials offer the advantage of greater dielectric constants than silicon oxide, so that a physically thicker dielectric will limit the gate tunneling current.
  BibTeX:
  @article{SAS+:IJE:2003,
  author = {A. Seekamp and A. Avellán and S. Schwantes and W. Krautschneider},
  title = {{S}imple estimation of the effect of hot-carrier degradation on scaled n{M}{O}{S}{F}{E}{T}s},
  year = {2003},
  month = {10},
  journal = {International Journal of Electronics},
  number = {10},
  pages = {607-12},
  volume = {90} }
  [Abstract] [BibTeX]
  
  
• R.R. Schliewe, F.A. Yildrim, W. Bauhofer, W. Krautschneider
  Deposition and characterization of polymeric layers for organic electronics
  In Tagungsband "Proc. Polytronic", 2003
  Montreux, Switzerland
  Abstract:
  This paper presents a detailed characterization of different thermosetting polymers to be used as gate dielectrics in organic thin-film transistors. Selected materials yield smooth films with good insulation properties and offer attractive processing conditions. Bottom-gate transistors were prepared using these dielectrics and compared to hybrid transistors with surface-treated SiO2 as the dielectric. Gate bias induced leakage and solvent effects were investigated by preparing metal/insulator/semiconductor devices. Poly(3-hexylthiophene) (P3HT) transistors with organic dielectrics exhibited higher channel conductivity and lower mobility values with respect to P3HT-hybrid transistors and pentacene transistors. The importance of dielectric/semiconductor interface was discussed by comparing the performances of pentacene and P3HT transistors produced on different dielectrics.
  BibTeX:
  @inproceedings{Schliewe:Yildrim:Bauhof,
  author = {R.R. Schliewe and F.A. Yildrim and W. Bauhofer and W. Krautschneider},
  title = {{D}eposition and characterization of polymeric layers for organic electronics},
  year = {2003},
  month = {10},
  booktitle = {Proc. Polytronic},
  note = {Montreux, Switzerland} }
  [Abstract] [BibTeX]
  
  
• R. Peck, D. Schroeder
  A low-power entropy-coding analog/digital converter with integrated data compression
  In Tagungsband "29th European Solid-State Circuits Conference (ESSCIRC 2003)", 2003, p. 173--176, Herausgeber J. Franca, R. Koch
  Estoril, Portugal, 16.-18. September 2003
  Abstract:
  A novel circuit architecture for integrated analog/digital converters (ADCs) is presented that allows to exploit the information-theoretic redundancy of the input signal for increasing the efficiency of operation. Analog/digital conversion and entropy-coding are combined in a single process such that integrated data compression as well as a low-power operation of the converter is obtained. A prototype ADC has been implemented in a 0.6 μm CMOS process. Experimental results showing the performance of the converter as well as the achieved compression ratios and power savings are discussed.
  BibTeX:
  @inproceedings{Peck:ESSCIRC:2003,
  author = {R. Peck and D. Schroeder},
  title = {{A} low-power entropy-coding analog/digital converter with integrated data compression},
  year = {2003},
  month = {09},
  booktitle = {29th European Solid-State Circuits Conference (ESSCIRC 2003)},
  editor = {J. Franca, R. Koch},
  note = {Estoril, Portugal, 16.-18. September 2003},
  pages = {173--176} }
  [Abstract] [BibTeX]
  
  
• R. Peck and D. Schröder
  Verringerung des Linearitätsfehlers eines 12-Bit-Charge-Redistribution-A/D-Wandlers
  In Tagungsband "ANALOG 2003", Verlag VDE-Verlag, 2003, vol. 177, Serie "ITG-Fachbericht", p. 191--195
  7. ITG/GMM-Diskussionssitzung, Heilbronn, 10.-12. September 2003
  Abstract:
  In diesem Beitrag wird über die Weiterentwicklung unseres Projektes zum Entwurf eines effizienten entropiecodierenden A/D-Wandlers (ECOC) berichtet. Nachdem durch Messungen am ersten Testchip insbesondere die Verzerrungen und das Rauschen der integrierten Schaltung experimentell bestimmt und entsprechende Schlussfolgerungen hinsichtlich eines Redesigns gezogen wurden, liegen nun Ergebnisse aus einem verbesserten Entwurf vor. Es wird ausführlich diskutiert, welche Schritte zur Verringerung des Linearitätsfehlers unternommen wurden. Messungen an den realisierten Chips zeigen, dass die Maßnahmen erfolgreich waren und tatsächlich zu einer höheren Linearität des Wandlers geführt haben.
  BibTeX:
  @inproceedings{Peck:LinearADC:2003,
  author = {R. Peck and D. Schr{\"o}der},
  title = {{V}erringerung des {L}inearit{\"a}tsfehlers eines 12-{B}it-{C}harge-{R}edistribution-{A}/{D}-{W}andlers},
  year = {2003},
  month = {09},
  booktitle = {ANALOG 2003},
  note = {7. ITG/GMM-Diskussionssitzung, Heilbronn, 10.-12. September 2003},
  pages = {191--195},
  publisher = {VDE-Verlag},
  series = {ITG-Fachbericht},
  volume = {177} }
  [Abstract] [BibTeX]
  
  
• D. Schröder and B. Fuchs and C. Bronskowski and W. Krautschneider
  Low Power Schaltkreise für die Medizinelektronik
  Artikel in "TU-Spektrum", p. 4, 2003
  Sommer 2003
  Abstract:
  Der Trend zu kleinen, leichten und mobilen Geraeten hielt auch in die Medizintechnik Einzug. Wo bisher EKG-Geraete auf Wagen gefahren und mit vielen Kabeln an den Patienten angeschlossen wurden, koennen diese nun in einer Aktentasche transportiert werden und die Signale drahtlos uebermitteln. Integrierte Schaltungen aus dem Arbeitsbereich Mikroelektronik spielen bei der Realisierung solcher Geraete eine zentrale Rolle.
  BibTeX:
  @article{Schr{\"o}der:TU-Spektrum:2003,
  author = {D. Schr{\"o}der and B. Fuchs and C. Bronskowski and W. Krautschneider},
  title = {{L}ow {P}ower {S}chaltkreise f{\"u}r die {M}edizinelektronik},
  year = {2003},
  month = {06},
  journal = {TU-Spektrum},
  note = {Sommer 2003},
  pages = {4} }
  [Abstract] [BibTeX]
  
  
• A. Avellán, E. Miranda, D. Schroeder, W. Krautschneider
  Unified model for the voltage and temperature dependence of the soft breakdown conduction mechanism in ultrathin gate oxides
  In Tagungsband "13th Conference on Insulating Films on Semiconductors", 2003
  Barcelona, 18-20 June 2003
  Abstract:
  The voltage and temperature dependence of the soft breakdown conduction mechanism in ultrathin gate oxides in MOS structures was investigated. Measurements performed on p- and n-type substrate samples with different oxide thickness were compared, and the results analyzed within the framework of the quantum point-contact model for dielectric breakdown. The model has been extended so as to include the thermal vibrations of the atoms that form the constriction's bottleneck. A new interpretation of the model parameters in connection with the potential drops distribution is also discussed.
  BibTeX:
  @inproceedings{AMS+:INFOS:2003,
  author = {A. Avellán and E. Miranda and D. Schroeder and W. Krautschneider},
  title = {{U}nified model for the voltage and temperature dependence of the soft breakdown conduction mechanism in ultrathin gate oxides},
  year = {2003},
  month = {06},
  booktitle = {13th Conference on Insulating Films on Semiconductors},
  note = {Barcelona, 18-20 June 2003} }
  [Abstract] [BibTeX]
  
  
• Stefan Schwantes and Ralf Göttsche and Wolfgang Krautschneider
  Impact of parasitic elements on the performance of digital CMOS circuits with Gigabit feature size
  Artikel in "Solid-State Electronics", vol. 47, p. 1243, 2003
  Abstract:
  This paper discusses the impact of the interconnect parameters on the signal delay of digital CMOS circuits. The minimum feature size for simulated MOSFETs was scaled in the range from 100 to 10 nm and interconnects were scaled down to 25 nm feature size. Our results show that new parasitic effects, as the size effect for copper and the increase of the threshold voltage due to direct tunneling gate current, will partly compensate the performance gain obtained by using new materials. These effects must be considered for minimum feature sizes below 50 nm. The influences have been studied on a logical unit and on on-chip interconnect scheme.
  BibTeX:
  @article{schwantes:2003,
  author = {Stefan Schwantes and Ralf G{\"o}ttsche and Wolfgang Krautschneider},
  title = {{I}mpact of parasitic elements on the performance of digital {C}{M}{O}{S} circuits with {G}igabit feature size},
  year = {2003},
  journal = {Solid-State Electronics},
  pages = {1243},
  volume = {47} }
  [Abstract] [BibTeX]
  
  
• B. Sell and A. Sänger and W. Krautschneider
  Interface analysis of atomic layer deposited-TiN gate electrodes on ultrathin SiO2 layers
  Artikel in "J. Vac. Sci. Technol.", vol. B21, p. 931, 2003
  Abstract:
  As new gate materials become increasingly interesting in conjunction with tunnel oxides. New deposition techniques have to be developed that deposit thin metal layers without degrading the gate dielectric. Recently, atomic layer deposition has been identified as a suitable method to deposit refractory metal alloys with well-defined properties. For the first time, a recently developed automated charcterization of capacitance-voltage (C-V) curves is employed to identify challeges during the initiation of a metal atomic layer deposition process. While some problems were eliminated by adapting the deposition process, others will require further process or tool modifications to reduce the nonuniformities abserved within each wafer. The temperature dependence of the C-V curves indicates an unintended titanium-rich layer at he interface, which disappears after annealing above 800°C. A further development of teh surface pretreatment and subsequent deposition will be neccessary to avoid this phenomenon. In this article, a very sensitive procedure to analyze the initiation of a metal atomic layer deposition process is presented.
  BibTeX:
  @article{Sell:Interf:03,
  author = {B. Sell and A. S{\"a}nger and W. Krautschneider},
  title = {{I}nterface analysis of atomic layer deposited-{T}i{N} gate electrodes on ultrathin {S}i{O}2 layers},
  year = {2003},
  journal = {J. Vac. Sci. Technol.},
  pages = {931},
  volume = {B21} }
  [Abstract] [BibTeX]
  
  
• A. Avellán, D. Schroeder, W. Krautschneider
  Modeling random telegraph signals in the gate current of metal oxide semiconductor field effect transistors after oxide breakdown
  Artikel in "Journal of Applied Physics", vol. 94, Nr. 1, p. 703-8, 2003
  Abstract:
  Measurements of random telegraph signals (RTS) in the gate curent of n-channel metal oxide semiconductor field effect transistors (MOSFETs) after oxide breakdown are presented. Two types of behavior of the time constants and the relative amplitudes of the signals as a function of gate voltage are observed. A theory relating time constants and relative amplitudes of the fluctuations to the energetic and geometric trap location in the oxide is developed. This theory is also applicable to the commonly observed RTS in the drain current of undamaged MOSFETs.
  BibTeX:
  @article{ASW:JAP:2003,
  author = {A. Avellán and D. Schroeder and W. Krautschneider},
  title = {{M}odeling random telegraph signals in the gate current of metal oxide semiconductor field effect transistors after oxide breakdown},
  year = {2003},
  journal = {Journal of Applied Physics},
  number = {1},
  pages = {703-8},
  volume = {94} }
  [Abstract] [BibTeX]
  
  
• D. Schroeder, A. Avellán
  Physical explanation of the barrier height temperature dependence in metal-oxide-semiconductor leakage current models
  Artikel in "Applied Physics Letters", vol. 82, Nr. 25, p. 4510-2, 2003
  Abstract:
  A temperature dependence of the barrier height between silicon and oxide has been proposed by many authors in order to reflect experimental metal-oxide-semiconductor leakage current results. However, no satisfactory physical explanation of this dependence has yet been given. In this paper, the temperature dependence of the observed macroscopic barrier height is explained by thermal fluctuations of the microscopic local barrier height. Because of the exponential relationship between current and barrier height, the decrease of the barrier during the fluctuation has a dominating effect when compared to the increase, leading on the average to a raised leakage current and correspondingly to a lowered average barrier height.
  BibTeX:
  @article{SA:APL:2003,
  author = {D. Schroeder and A. Avellán},
  title = {{P}hysical explanation of the barrier height temperature dependence in metal-oxide-semiconductor leakage current models},
  year = {2003},
  journal = {Applied Physics Letters},
  number = {25},
  pages = {4510-2},
  volume = {82} }
  [Abstract] [BibTeX]
  
  
• A. Avellán, E. Miranda, B. Sell, W. Krautschneider
  Experimental study and modeling of the temperature dependence of soft breakdown conduction in ultrathin gate oxides
  In Tagungsband "41st International Reliability Physics Symposium", 2003, p. 580-1
  41st International Reliability Physics Symposium
  Abstract:
  Despite the many efforts devoted to improve our understanding of the physics of soft breakdown (SBD) conduction in ultrathin gate oxides, there are still some aspects of the phenomenon which have been rather overlooked and that are relevant for assessing the adequacy of the addressed transport mechanism. In particular, in this work, we focus our interest on the temperature dependence of SBD, mainly in the range in which real devices are commonly operated (-20°C to 160°C). A thorough experimental study involving samples with different oxide thicknesses and substrate types is presented, and the results are interpreted in terms of an extended version of the quantum point contact model (QPC) for the non-zero temperature case. Even though several approaches attempting to explain the SBD I-V characteristics have been proposed, analytical modeling of its temperature dependence has always been restricted to a single bias condition. In contrast, we provide a simple parameterization of the experimental data which accounts for both characteristics, I-V and I-T, within a consistent framework based on the physics of mesoscopic conductors. As we show below, the magnitude of the current flowing through the SBD spot essentially depends on the barrier height encountered by the incoming electrons, while the shape of the I-V characteristic is dictated by the particular features of the spot and the potential drops distribution. The model's suitability for circuit simulation opens the perspective to determine post breakdown circuit behavior and the impact of soft breakdown on specific applications.
  BibTeX:
  @inproceedings{AMS+:IRPS:2003,
  author = {A. Avellán and E. Miranda and B. Sell and W. Krautschneider},
  title = {{E}xperimental study and modeling of the temperature dependence of soft breakdown conduction in ultrathin gate oxides},
  year = {2003},
  booktitle = {41st International Reliability Physics Symposium},
  note = {41st International Reliability Physics Symposium},
  pages = {580-1} }
  [Abstract] [BibTeX]
  
  
• S. Schwantes, W. Krautschneider
  Temperature effects in sub 50 nm CMOS circuits
  In Tagungsband "Proc. 4th European Workshop on Ultimate Integration of Silicon, ULIS", 2003
  ULIS 2003
  Abstract:
  This paper discusses the impact of the supply voltage and the threshold voltage on the temperature behavior of digital circuits with sub 50 nm feature sizes. For low supply voltages a positive temperature dependence of the drain current and the circuit speed can be observed. This is different from the common negative temperature dependence in conventional designs. The theory of this effect is discussed using test structures and device simulations. It is shown that a hazardous positive feedback may occur for low voltage technologies. This can lead to temperature instabilities for large circuits with very small feature sizes.
  BibTeX:
  @inproceedings{Schwantes:Temperature:03,
  author = {S. Schwantes and W. Krautschneider},
  title = {{T}emperature effects in sub 50 nm {C}{M}{O}{S} circuits},
  year = {2003},
  booktitle = {Proc. 4th European Workshop on Ultimate Integration of Silicon, ULIS},
  note = {ULIS 2003} }
  [Abstract] [BibTeX]
  
  

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