2002

• S. Schwantes and W. Krautschneider
  Performance improvement of metal gate CMOS technologies with gigabit feature sizes
  In Tagungsband "Proc. 5th Annual Workshop on Future Electronics SAFE", 2002
  Eindhoven, The Netherlands, 2002
  Abstract:
  Abstract—For the first time we have investigated the impact of metal gates on the performance of large digital circuits by simulations. So far, the impact of metal gates has just been discussed on small circuits and single transistors [1]. The performance improvement is discussed based on the simulation of a simple ring oscillator and a 64bit adder for CMOS technologies with 100 nm to 10 nm feature sizes. The integration of metal gates allows a performance increase of large digital circuits by more than 33% for the 25 nm generation whereas small circuits like ring oscillators show no improvement. Metal gates are also helpful in the reduction of the total power consumption. A reduction of the total power consumption by 28% has been observed for the 64bit adder for smallest feature sizes. Even though the integration of metal gates into the standard CMOS process is still complicated it offers the potential to increase the performance significantly.
  BibTeX:
  @inproceedings{Schwantes:SAFE02,
  author = {S. Schwantes and W. Krautschneider},
  title = {{P}erformance improvement of metal gate {C}{M}{O}{S} technologies with gigabit feature sizes},
  year = {2002},
  month = {11},
  booktitle = {Proc. 5th Annual Workshop on Future Electronics SAFE},
  note = {Eindhoven, The Netherlands, 2002} }
  [Abstract] [BibTeX]
  
  
• A. Avellán, E. Miranda, B. Sell, D. Schroeder, W. Krautschneider
  Temperature dependence of the hard breakdown current of MOS capacitors
  In Tagungsband "32nd European Solid-State Device Research Conference", 2002, p. 463-6
  32nd European Solid-State Device Research Conference
  Abstract:
  I-V curves as a function of temperature of broken down n- and p-type MOS capacitors with different oxide thicknesses are presented. In accumulation, a crossover of the temperature dependent curves is observed. At low voltages the hard breakdown current increases with temperature whereas it decreases with temperature for higher voltages. This behaviour can be straightforwardly linked to the available charge for conduction at the electrodes. MINIMOS simulations as well as theoretical considerations were performed that clearly support this idea. The presentation can be found at: http://www.essderc2002.deis.unibo.it/ESSDERC_web/Session_D22/D22_3.pdf
  BibTeX:
  @inproceedings{AMS+:ESSDERC:2002,
  author = {A. Avellán and E. Miranda and B. Sell and D. Schroeder and W. Krautschneider},
  title = {{T}emperature dependence of the hard breakdown current of {M}{O}{S} capacitors},
  year = {2002},
  month = {09},
  booktitle = {32nd European Solid-State Device Research Conference},
  note = {32nd European Solid-State Device Research Conference},
  pages = {463-6} }
  [Abstract] [BibTeX]
  
  
• R. Peck and D. Schröder
  Entwurf und Test eines mit sukzessiver Approximation arbeitenden 12-Bit-A/D-Wandlers
  In Tagungsband "ANALOG 2002", Verlag VDE-Verlag, 2002, vol. 38, Serie "GMM-Fachbericht", p. 331-336
  6. GMM/ITG-Diskussionssitzung, Bremen, 13.-14. Mai 2002
  Abstract:
  In diesem Beitrag wird über den aktuellen Zwischenstand unseres Projektes zum Entwurf eines effizienten entropie-codierenden A/D-Wandlers (ECOC) berichtet. Grundsätzliche Überlegungen zur Architektur des Analogteils führen zu einem Trade-Off zwischen Verlustleistung und Chipfläche, so dass eine optimale Wahl der Strukturparameter getroffen werden kann. Nach einigen Angaben zum Chiplayout wird ausführlich auf die Messergebnisse des ersten Testchips eingegangen, bei dem insbesondere die Verzerrungen und das Rauschen der integrierten Schaltung experimentell bestimmt wurden. Aus den Messergebnissen können Schlussfolgerungen hinsichtlich der Fehlerursachen in der Designphase und ent-sprechende Maßnahmen beim Redesign gezogen werden.
  BibTeX:
  @inproceedings{Peck:TestADC:2002,
  author = {R. Peck and D. Schr{\"o}der},
  title = {{E}ntwurf und {T}est eines mit sukzessiver {A}pproximation arbeitenden 12-{B}it-{A}/{D}-{W}andlers},
  year = {2002},
  month = {05},
  booktitle = {ANALOG 2002},
  note = {6. GMM/ITG-Diskussionssitzung, Bremen, 13.-14. Mai 2002},
  pages = {331-336},
  publisher = {VDE-Verlag},
  series = {GMM-Fachbericht},
  volume = {38} }
  [Abstract] [BibTeX]
  
  
• A. Avellán, W. Krautschneider
  On-Chip-Stromverstärker zur Messung von Signalen im Zeitbereich
  In Tagungsband "Analog 2002", Verlag VDE Verlag, 2002, vol. 38, Serie "GMM-Fachbericht", p. 145-9
  Analog 2002
  Abstract:
  Es wird ein stromrückgekoppelter Operationsverstärker vorgestellt, mit dem Ströme eines zu untersuchenden MOS-Transistors direkt auf dem Chip verstärkt und strom-spannungsgewandelt werden. Die verstärkten Ströme können mit einfacherer Meßtechnik erfaßt beziehungsweise deren zeitlicher Verlauf problemlos mit einem Oszilloskop aufgenommen werden. Dies wird am Beispiel von Fluktuationen im Sourcestrom des MOS-Transistors beispielhaft aufgezeigt.
  BibTeX:
  @inproceedings{AK:Analog:2002,
  author = {A. Avellán and W. Krautschneider},
  title = {{O}n-{C}hip-{S}tromverst{\"a}rker zur {M}essung von {S}ignalen im {Z}eitbereich},
  year = {2002},
  month = {05},
  booktitle = {Analog 2002},
  note = {Analog 2002},
  pages = {145-9},
  publisher = {VDE Verlag},
  series = {GMM-Fachbericht},
  volume = {38} }
  [Abstract] [BibTeX]
  
  
• S. Vogel and D. Schröder
  Systematischer Entwurf von Operationsverstärkern für minimale Verlustleistung bei gegebenen Rauschanforderungen
  In Tagungsband "ANALOG 2002", Verlag VDE-Verlag, 2002, vol. 38, Serie "GMM-Fachbericht", p. 297-301
  6. GMM/ITG-Diskussionssitzung, Bremen, 13.-14. Mai 2002
  Abstract:
  Für aktive RC-Filter wird der Zusammenhang zwischen Verlustleistung und Signal/Rausch-Verhältnis (SNR) in Abhängigkeit der frei wählbaren Schaltungsparameter untersucht. Dabei wird der Zusammenhang von Rauschen und Verlustleistung des verwendeten Operationsverstärkers (OpAmp) modellmäßig berücksichtigt. Hierdurch kann einerseits die externe Beschaltung des OpAmp so dimensioniert werden, dass bei möglichst geringer Leistungsaufnahme ein gefordertes SNR erreicht wird. Gleichzeitig kann der OpAmp selbst auf die Anwendung hin optimiert werden. Weiterhin kann vorab eine untere Grenze der Leistungsaufnahme ermittelt werden, um z.B. die prinzipielle Machbarkeit einer Aufgabenstellung abzuschätzen.
  BibTeX:
  @inproceedings{Vogel:OP-Entwurf:2002,
  author = {S. Vogel and D. Schr{\"o}der},
  title = {{S}ystematischer {E}ntwurf von {O}perationsverst{\"a}rkern f{\"u}r minimale {V}erlustleistung bei gegebenen {R}auschanforderungen},
  year = {2002},
  month = {05},
  booktitle = {ANALOG 2002},
  note = {6. GMM/ITG-Diskussionssitzung, Bremen, 13.-14. Mai 2002},
  pages = {297-301},
  publisher = {VDE-Verlag},
  series = {GMM-Fachbericht},
  volume = {38} }
  [Abstract] [BibTeX]
  
  
• B. Sell, A. Avellán, W. H. Krautschneider
  Charge-Based Capacitance Measurements (CBCM) on MOS Devices
  Artikel in "IEEE Transactions on Device and Materials Reliability", vol. 2, Nr. 1, p. 9-12, 2002
  Abstract:
  A new simple method of measuring capacitance-voltage characteristics of MOS devices is presented. Proceeding from the charge-based capacitance measurement technique suggested recently, a compact test structure with high resolution has been developed, which only requires measurement of dc quantities. The method was tested on a 0.6-µm CMOS process with small and large area capacitors and compared to well-known high-frequency capacitance-voltage results. Beside using a reference structure, a second means of extracting parasitic effects is demonstrated for small structures. The test structure allows measurements in a wide frequency range with high accuracy and low noise contribution at small capacitance levels.
  BibTeX:
  @article{SAK:TDMR:2002,
  author = {B. Sell and A. Avellán and W. H. Krautschneider},
  title = {{C}harge-{B}ased {C}apacitance {M}easurements ({C}{B}{C}{M}) on {M}{O}{S} {D}evices},
  year = {2002},
  month = {01},
  journal = {IEEE Transactions on Device and Materials Reliability},
  number = {1},
  pages = {9-12},
  volume = {2} }
  [Abstract] [BibTeX]
  
  
• B. Sell and D. Schumann and W.H. Krautschneider
  Fast interface characterization of tunnel oxide MOS structures
  Artikel in "IEEE Transactions on Nanotechnology", Nr. 1, p. 110, 2002
  Abstract:
  As new gate materials become increasingly interesting in conjuction with tunnel oxides, a fast and reliable interface characterization technique becomes indispensable. Fast turnaround times require a method which can be applied to simple test structures like planar capacitors. For the fist time, we demonstrate an automatic extreaction of physical oxide thickness and flatband potential from capacitance-voltage measurements which includes quantum confinement effects and Fermi-Dirac statistics. Automatic extraction is necessary for uniformity analysis across a whole wafer. New gate materials are typically binary or ternary alloys where the interface to the gate dielectric is very sensitive to deposition parameters. Such saystems are likely to show higher nonuniformities than polysilicon electrodes. An example is presented where polysilicon gates exhibit a uniformity in flatband potential within a wafer of less than ± 15 mV while a thickness variation of 0.1 nm has been observed.
  BibTeX:
  @article{Sell:IEEE:2002,
  author = {B. Sell and D. Schumann and W.H. Krautschneider},
  title = {{F}ast interface characterization of tunnel oxide {M}{O}{S} structures},
  year = {2002},
  journal = {IEEE Transactions on Nanotechnology},
  number = {1},
  pages = {110} }
  [Abstract] [BibTeX]
  
  
• B. Sell and A. Saenger and W. Krautschneider
  Interface Analysis of ALD-TiN Gate-Electrodes on Ultrathin Si02 Layers
  Artikel in "Vacuum Science and Technology B", 2002
  Abstract:
  
  BibTeX:
  @article{Sell:ALD-TiN:2002,
  author = {B. Sell and A. Saenger and W. Krautschneider},
  title = {{I}nterface {A}nalysis of {A}{L}{D}-{T}i{N} {G}ate-{E}lectrodes on {U}ltrathin {S}i02 {L}ayers},
  year = {2002},
  journal = {Vacuum Science and Technology B} }
  [BibTeX]
  
  
• B. Fuchs, S. Vogel, D. Schroeder
  Universal application-specific integrated circuit for bioelectric data acquisition
  Artikel in "Medical Engineering & Physics", vol. 24, p. 695--701, 2002
  Abstract:
  Use of highly integrated application specific circuits (ASICs) in bioelectric data acquisition systems promise important new insights into the origin of a large variety of health problems by providing light-weight, low-power, low-cost medical measurement devices that allow longterm studies. They also promise significant cost reduction in medical care, as patients in principle become mobile and do not have to be hospitalized for observation. We report on the development and successful implementation of a universal ASIC, designed to meet key characteristics of a broad variety of bioelectric signals in terms of their dynamic range, sampling rate and input referred noise; e. g. Electrocardiogram (ECG), Electroencephalogram (EEG) and, most constringently, Evoked Potentials (EP). Our approach for the first time makes cost-effective use of state-of-the-art microelectronics in medical measurement equipment, thus offering to replace discrete, single application devices used at present.
  BibTeX:
  @article{Fuchs:ASEEG:2002,
  author = {B. Fuchs and S. Vogel and D. Schroeder},
  title = {{U}niversal application-specific integrated circuit for bioelectric data acquisition},
  year = {2002},
  journal = {Medical Engineering {&} Physics},
  pages = {695--701},
  volume = {24} }
  [Abstract] [BibTeX]
  
  
• S. Schwantes and W. Krautschneider
  Impact of Parasitic Elements on the Performance of Digital CMOS Circuits with Gigabit Feature Size
  In Tagungsband "Proc. 3rd European Workshop on Ultimate Integration of Silicon, ULIS", 2002, p. 49
  ULIS 2002
  Abstract:
  
  BibTeX:
  @inproceedings{Schwantes:ULIS:2002,
  author = {S. Schwantes and W. Krautschneider},
  title = {{I}mpact of {P}arasitic {E}lements on the {P}erformance of {D}igital {C}{M}{O}{S} {C}ircuits with {G}igabit {F}eature {S}ize},
  year = {2002},
  booktitle = {Proc. 3rd European Workshop on Ultimate Integration of Silicon, ULIS},
  note = {ULIS 2002},
  pages = {49} }
  [BibTeX]
  
  

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